Chelsio Communication is looking at hiring new grads for Hardware(RTL Verification & Design) team. We are looking for people with Basic knowledge in Digital Logic design and Computer architecture.
Requirements: Good communications skills, both verbal and writing.
BE/BTech or ME/MTech with a minimum of 0-5 years experience in
relevant area
1: Specification development
o Capture and analysis of design requirements
o Creation of functional verification plan based on requirements
o Identification of suitable IP blocks and create specifications for BFM/Stub development.
o IC architecture development (block architecture, interfaces, etc.)
2: Developing a robust
verification plan and environment with different methodologies
o Specification to model testbench
o Architecting layered, Class based automated testbenches
o Hands-on development experience with Constrained Random test-bench using High Level Verification Languages(SystemVerilog/VERA preferred)
o Deploying SystemVerilog assertions (SVA) or OpenVera assertions (OVA)
o Developing and integrating verification IP
o Experience in verification environment development using OVM/VMM/UVM
o Emulation / silicon validation experience is plus o Strong knowledge on Perl, UNIX shell, or equivalent scripting languages
o Generating and Analyzing Code Coverage reports.
3: Domain knowledge o PCIE or MAC or DDR or Networking protocols work experience o Security experience is plus
o PowerPC or MIPS or Tensilica processor knowledge o TCP, RDMA, FCOE, iSCSI
Requirements: Good communications skills, both verbal and writing.
BE/BTech or ME/MTech with a minimum of 0-5 years experience in
relevant area
1: Specification development
o Capture and analysis of design requirements
o Creation of functional verification plan based on requirements
o Identification of suitable IP blocks and create specifications for BFM/Stub development.
o IC architecture development (block architecture, interfaces, etc.)
2: Developing a robust
verification plan and environment with different methodologies
o Specification to model testbench
o Architecting layered, Class based automated testbenches
o Hands-on development experience with Constrained Random test-bench using High Level Verification Languages(SystemVerilog/VERA preferred)
o Deploying SystemVerilog assertions (SVA) or OpenVera assertions (OVA)
o Developing and integrating verification IP
o Experience in verification environment development using OVM/VMM/UVM
o Emulation / silicon validation experience is plus o Strong knowledge on Perl, UNIX shell, or equivalent scripting languages
o Generating and Analyzing Code Coverage reports.
3: Domain knowledge o PCIE or MAC or DDR or Networking protocols work experience o Security experience is plus
o PowerPC or MIPS or Tensilica processor knowledge o TCP, RDMA, FCOE, iSCSI
Interested people forward your resume to hpshenoy@gmail.com
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