Memory Layout Engineer

Hi, 
We have following requirements. 
********************************** 
Memory Design /Characterization Engineer 
********************************** 
2-12YEARS 
LOCATON :BANGALORE,NOIDA 

Candidate must have transistor level circuit design experience of memories. 
He/She should have worked on 65nm / 45nm / 28nm process technologies and must have Understanding of design issues related to process. 
Candidate is expected to work as individual contributor on memory characterization projects. Understanding of memory critical paths and characterization tools. 
Candidate must have done logic verification of memories using verilog or ESPCV. 
Candidate must have significant exposure to validation of the characterized data and undertaken at least few memory compilers or instances. 
Candidate must have transistor level circuit design experience of memories. 

******************** 
Memory Layout Engineer 
********************** 
3-8years 
LOCATON :BANGALORE,NOIDA 
Candidate must have experience in layout design of memory leaf cells and at top level of memories should have worked on 65nm / 45nm / 28nm process technologies and Good understanding of issues like WPE, LOD effects. He/She must have good understanding of physical verification checks. DRC, LVS, ERC and reliability checks . IR and EM 

If you wish to apply send the profile to jaya@ieipl.net 

Regards, 
JAYA 
IEIPL 
BANGALORE 

Please connect to me in the following networks 

t: | e: jaya@ieipl.net | 
w: linkedin.com/pub/jaya-lakshmi/15/914/82